The majority of consumer products today use high speed digital processing to improve feature sets and product quality, such as digital video (DV.) However the sensor interface to these products is generally of an analog nature, thus a conversion from analog to digital domains is required. To attain the perceived high quality of the product, the converted data must also be of high quality and therefore high-resolution high-speed converter devices are required. These analog to digital converters (ADCs) convert the analog signals from sensors or transducers, such as charge-coupled devices (CCD) into digital format for later digital signal processing.
Although many different architectures of ADCs exist, such as flash, two-step and pipelined, the optimal architecture for power-resolution-size-cost is based on switched capacitor techniques. The use of switched capacitor design allows high resolution ADCs with moderate speeds with small die areas. The core of a switched capacitor design is an operational amplifier (Op-amp). The characteristics of the Op-amp determine the switched capacitor performance and thus ADC overall performance. The Op-amp must possess the following characteristics. It should also be noted while the Op-amp is herein defined with respect to ADC design, the following Op-amp needs can also be attributed to any switched capacitor circuit application.
Switched capacitor design relies on the switching of capacitors in feedfoward and feedback arrangements around an Op-amp with Gain, to cause charge movement from one element to another. Switched capacitor filters, gain stages, sample-and-holds, are typically designed around how the capacitors are arranged and the timing and order they are switched. To ensure maximal charge movement between elements, the Op-amp gain needs to be extremely high (from basic Op-amp theory.) For the purposes of high resolution ADCs, in excess of 70 dB DC gain is normally required.
The speed at which the ADC can start to sample, convert and then transfer its digital representation to the digital section is termed its conversion time. In a switched capacitor converter design, this conversion time is mainly defined by how fast the Op-amp settles to its final value to within a defined accuracy. High resolution high speed converters require short settling times in the order of nanoseconds to within 0.1% final accuracy or better.
Due to the handheld nature of a significant number of consumer products, battery life is paramount, thus ADC device power dissipation should be minimal. This can be minimized by system architecture, such as with switched capacitor pipelined ADC over Flash ADC. However, in the switched capacitor circuit, the defining single power dissipater is the Op-amp. The reason for this is based on the general laws of physics, which require charge to be moved from one capacitor to another. The more charge to be transferred, the more power is dissipated. Also, the more often or frequent the charge transfer occurs also determines that more power is dissipated. High-speed high-resolution converters require large capacitors to lower noise (kT/C noise) and increase resolution, thus large charge transfers are required. Also high speeds require fast conversion times, which equates to fast settling (high speed) to high final accuracy (high resolution.) Again, this means significant power is required.
The lifecycles of consumer products are generally short and also tend to be competitive, thus product volumes should be high, while general margins are driven low by market demands. This requires high yields from all devices in the product so that margins can be attained. Switched capacitor circuits due to their inherent use of a reference clock, mean that their overall performance stability is significantly higher than pure analog approaches. However, the analog components within a switched capacitor circuit will still be affected by process, temperature and voltage variations and thus can reduce yields. The main yield definer in the switched capacitor circuit is the Op-amp as this is the single biggest analog sub-block in the converter design. To thus attain high yield of the ADC device, the Op-amp should be insensitive to process, temperature and voltage variations.
The useful resolution of an ADC is determined by its dynamic range, which defines the difference between the largest and smallest signals that it can process. A number of factors define dynamic range such as supply voltage and ADC architecture. The power supply voltages and how near the Op-amp's voltage outputs can swing towards these voltages define large signal handling. The use of fully differential Op-amp designs helps increase large signal handling. The lower signal handling is defined by capacitor noise (kT/C) and Op-amp input referred noise. Again, differential design of the Op-amp is also beneficial in rejection of common-mode noise. As such, the Op-amp is a key element in defining the dynamic range of the ADC. The Op-amp should have large signal handling capability, but with low noise.
Consumer products require large volumes, while competitive products and customer demands force low margins. As such, for a product to be successful in a market, it must attain high yields while being cheap to manufacture. This is true for all sub-blocks and as such the die size of the ADC should be small. As the switched capacitor Op-amps and capacitors are a significant size in the overall ADC layout, size reduction of these elements equates to lower overall final cost of the ADC and the final product. Smaller die size also helps in reducing packaging costs, with the inherent cost savings.
High resolution ADCs are needed for consumer and other product groups. In switched capacitor ADC design, the Operational Amplifier (Op-amp) is the key-defining element affecting overall ADC performance and cost. The Op-amp should have high gain, fast settling to a high final accuracy, low power dissipation, capable of driving large capacitive loads, have high yields, handle large and small signals to obtain high dynamic range, be differential to aid in noise suppression and improve dynamic range, while being physically small to lower die size and reduce costs.
Generally speaking, all the above criteria can be met, however each target would normally be achieved by increasing power dissipation. In fact, present operational amplifiers in switched capacitor circuits can not meet all of the above criteria without increasing the power dissipation.
Normally to meet the needs as defined above, a single stage folded-cascode differential Op-amp with gain-enhancement is utilized. However, this design wastes current in the folding and would require additional current for a single switched capacitor gain stage. To reduce the current consumption and achieve 100% power efficiency, a stacked telescopic gain-enhanced architecture is more preferable. Such a telescopic Op-amp of the prior art is depicted in FIG. 1. The anticipated current consumption for this type of architecture is 3.7 mA @ 3V for a telescopic design running at sub 100 Msps. The disadvantages are headroom issues due to the stacking, thus control of the common-mode input and output levels is important, as well as the bias points of the gain-enhancement stages.
Different solutions have been attempted to improve over the telescopic Op-amp design, which is known to one skilled in the art as a Classic Class A design. In Class AB designs, the bias current of the amplifier is increased in proportion to the amplitude of the input signal. The advantage of this technique is that the charge to be transferred in the switched capacitor circuit is related to the input signal voltage. As such, for small voltage swings, small charge transfers are required, thus lower bias currents can be used. The disadvantage is that the amplifier must react on a sample to sample basis and change its bias current accordingly. As the amplitude of two adjacent samples could span the whole dynamic range, the amplifier bias system must react fast without affecting settling.
Further prior art solutions include reducing the power using a form of self-correcting biasing, which is integrated into the Common-Mode Feedback (CMFB) system. The advantage as expected is lower power dissipation. However, this is outweighed by the fact that CMFB and bias loops due to loop dynamics must meet stability criteria, which normally adversely affects settling time.
In further prior art solutions, dynamic current biasing is used to increase the Op-amp current in the sample phase and decrease current in the hold phase of a switched capacitor circuit operation. As this is timed from the switched capacitor clock, it does not involve any loops and is thus easy to implement. However, no CMFB is implemented and the CMFB loop will affect the settling time of the Op-amp as the bias current is changed. This is due to the inherent CMFB loop having to be stable to ensure a differential pair will work correctly with phase margin. Also, multi-stage folded designs waste current due to extra current branches and increase parasitic capacitances. This in-turn increases power dissipation and reduces maximum frequency of operation.
In further prior art solutions, a pseudo differential cascode amplifier, also termed a grounded source amplifier is utilized. This design has the advantage of having the current sink removed, thus allowing more headroom, greater swing and increased dynamic range. The design also shows how the CMFB circuit can be removed and the inherent switched capacitor circuit can be used to set the common-mode levels of the amplifier. The disadvantage of this design is a reduction in common-mode rejection ratio. Compared to a telescopic design, the power dissipation is the same, thus no power reduction techniques have been employed apart from removing the CMFB circuit.
Further embodiments employ dynamic current biasing in a folded cascode Op-amp using a differential pair. As per the normal telescopic design, the issues here are slow settling times related to CMFB loop dynamics. For low frequencies of operation this technique and a differential input stage is acceptable, but where fast settling is required, then CMFB interaction limits the overall performance. However, the main advantage is a significant decrease in overall current, as the current is modulated relative to the switched capacitor mode.
Further embodiments achieve high gain with the use of regulated cascades. This gain enhancement technique allows gains in excess of 70 dB while only using 1 gain stage. The advantage of this is that the overall power dissipation is lowered as only a single stage is required. Also, the settling time is improved due to reduced parasitics. The disadvantage is that the designs are more focused on gain enhancement, so although current is saved, they are still based on a folded input stage, and thus current is wasted in the folding.
Another technique is the use of switched capacitor biased Op-amps. Here the input stage current sink is replaced with a capacitor. During the hold phase the capacitor is disconnected and charged to a potential, and during the sampling phase, the capacitor is reconnected to the input pair. When the capacitor is first connected, the input pair can supply a significant amount of current before the capacitor charge is reduced. The amplifier can thus drive significant capacitive loads. As the bias capacitor charge reduces, the input pair gm increases until just as the capacitor charge is almost zero, where the gm is maximal (gm proportional to 1/I). As such, extremely high gains are achieved. Thus the ability to drive large capacitive loads (also gives good settling) with high gain and reduced power is achieved. The disadvantage is that the present Op-amps are single-ended, as fully differential designs require CMFB, which is significantly affected by the extreme current variations in the input pair during the bias capacitor charge/discharge cycle.
Referring back to the telescopic Op-amp of FIG. 1, a number of approaches have been attempted to reduce the telescopic Op-amp power dissipation further, including bias line pumping among others, but the majority affect the Common-Mode Feedback circuit. The most promising approach appears to be based on dynamically changing the Op-amp standing current in its sampling, amplification and holding operations. By doing this, the telescopic 3.7 mA standing could be reduced to approx 1.975 mA average (assuming a 50% duty cycle and 3.7 mA/250 uA for amplify/hold.) The implementation involves having additional current sink/sources in the Op-amp, which are switched on and off when power is required or can be saved.
Simulation results of the dynamic biased telescopic Op-amp show that to achieve a switched capacitor settling time of <10 ns, that the timing error when dynamically changing the current, should be no more than 100 ps and that the current match between sinks/sources should be 1% or better. The reason for this is that the current sink can turn on just before the sources or vice-versa, and cause the common-mode output voltage to change. This output voltage perbutation is evident as a settling response dominated by the CMFB characteristics. The CMFB is also affected by mismatch in sink source currents, as the CMFB corrects for any discrepancy in current between sinks and sources and again shows itself as a settling response in the outputs.
Thus far, the transistor level circuits attempting to implement a less than 1% match in sink/source with a timing error less than 200 ps have not been achieved. This can be attributed mainly due to the fact that achieving these goals requires complex circuits, which in-turn dissipates power. Thus, the overall reduction in power is reduced while its complexity and size increase significantly. As such, use of the telescopic gain enhanced dynamic biased Op-amp is not feasible.
As such, no techniques have as yet been devised to give low power dissipation while ensuring fast settling times and high dc gain of the switched capacitor fully differential Op-amp.